The present invention relates to data communication, and more particularly to communication between devices within a system.
Most computer systems are formed of components coupled together using one or more buses, which are used to transmit information between the various system components. Present bus standards such as the Peripheral Component Interconnect (PCI) Specification, Rev. 2.1 (published Jun. 1, 1995) provide a multi-drop bus in which multiple devices may be coupled to the same bus. Accordingly, it is easy to read or write to devices on the same bus.
However, as bus interface speeds increase, bus architectures are moving away from multi-drop architectures towards point-to-point architectures. In such point-to-point architectures, peer-to-peer communication becomes more difficult, as synchronization, ordering, and coherency of such communications becomes more difficult. One example of point-to-point architecture is a PCI Express™ architecture in accordance with the PCI Express Base Specification, Rev. 1.0 (published Jul. 22, 2002).
Because multiple buses of a system or coupled thereto may use different communication protocols, communications difficulties exist. For example, peer-to-peer communication between input/output (I/O) devices may be sent according to a first protocol, but due to the point-to-point architecture and secondary protocols used by other components between the I/O devices, such communication becomes difficult.
Further, I/O interfaces typically identify transactions as either posted and non-posted, and the ordering rules for each type differ. Certain ordering rules are in place for functional correctness (such as read transactions cannot pass write transactions, writes cannot pass writes, and the like). In addition to such ordering rules, certain protocols, such as PCI, require posted cycles to progress past stalled non-posted cycles. This is to avoid deadlocking the interface due to a lack of forward progress. In certain protocols, such as PCI, forward progress is enabled by allowing a target to “retry” the request, which signals to the initiator that it should bypass the attempted transaction and try another that might be behind it.
However, where I/O devices of a first protocol are coupled to a system having a second protocol, different methods exist for avoiding deadlocks, and sometimes these different mechanisms are not compatible. Such incompatibilities particularly exist when one protocol does not provide for retry options, and credit tracking of transactions is done at different layers of different protocols. Accordingly, a need exists to provide for deadlock-free transfer of transactions through a system, where multiple protocols exist for different components of the system.